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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
July 2001 Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107 Specification Revision History Version 0.0 Original Content Date July.2001
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
CONTENTS
INTRODUCTION ............................................................................................................................................. 1 BLOCK DIAGRAM .......................................................................................................................................... 2 PIN CONFIGURATION .................................................................................................................................... 3 100-QFP.................................................................................................................................................. 3 PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP).................................................................................... 4 PAD CENTER COORDINATES (100QFP)................................................................................................... 5 100-TQFP (S6B2107)................................................................................................................................ 6 PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP)................................................................................. 7 PAD CENTER COORDINATES (100-TQFP)................................................................................................ 8 PIN DESCRIPTION ........................................................................................................................................10 ELECTRICAL CHARACTERISTICS .................................................................................................................13 DC CHARACTERISTICS ..........................................................................................................................13 AC CHARACTERISTICS (VDD = 5V 10%, TA = -30C to +85C)..............................................................14 FUNCTIONAL DESCRIPTION ...................................................................................................................17 TIMING DIAGRAM .........................................................................................................................................19 1/48 DUTY TIMING (MASTER MODE).......................................................................................................19 1/128 DUTY TIMING (MASTER MODE).....................................................................................................20 1/48 DUTY TIMING (SLAVE MODE)..........................................................................................................21 POWER DRIVER CIRCUIT.......................................................................................................................22 APPLICATION CIRCUIT ...........................................................................................................................23
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
INTRODUCTION
The S6B0107 (TQFP type: S6B2107) is a LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver - TQFP type: S6B2108). The S6B0107 is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver).
FEATURES
-- -- -- -- -- -- -- -- Dot matrix LCD common driver with 64 channel output 64-bit shift register at internal LCD driver circuit Internal timing generator circuit for dynamic display Selection of master/slave mode Applicable LCD duty: 1/48, 1/64, 1/96, 1/128 Power supply voltage: + 5V 10% LCD driving voltage: 8V - 17V (V DD-VEE) Interface Driver COMMON Other S6B0107 SEGMENT S6B0108
Controller MPU
-- --
High voltage CMOS process 100QFP/100TQFP and bare chip available
1
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
C62 C63 C64
V0L V1L V4L V5L
C1 C2 C3
64 bit 4- Level Driver
V0R V1R V4R V5R
64 bit Bi-Directional Shift Register
DIO1 PCLK2 SHL
Data Shift Direction & Phase Selection Control Circuit
DIO2
M CL2
C R CR
OSC
Timing Generator Circuit
FRM CLK1 CLK2
VDD
DS1
DS2
VSS
VEE
2
MS
S
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PIN CONFIGURATION
100-QFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42
C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S6B0107
(100-QFP)
C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R NC CL2 NC
DS1 DS2 C R CR SHL VSS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2
31 32 33 35 37 39 40 41 42 43 44 45 46 47 48 49 50
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP)
C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43
Y
(0, 0)
X
Chip size: 3450 x 4000 PAD size: 100 x 100 Unit : m
S6B0107
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R
VDD 28
VSS 40
MS 42
FS 30
M 47
C 33
R 35
DS1 31
DS2 32
SHL 39
CLK2 43
CLK1 44
DIO1 29
FRM 46
There is the mark S6B0107 on the center of the chip.
4
PCLK2 49
DIO2 50
CL2 52
CR 37
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PAD CENTER COORDINATES (100QFP)
Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pad Name C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DI01 FS DS1 Coordinate X -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -977.6 -827.6 Y 1775.4 1630 1505 1380 1255 1130 1005 880 755 630 505 380 255 130 5 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 Pad Number 32 33 35 37 39 40 42 43 44 46 47 49 50 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pad Name DS2 C R CR SHL VSS MS CLK2 CLK1 FRM M PCLK2 DI02 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 Coordinate X -677.6 -527.6 -377.6 -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 Y -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 5 130 255 380 505 Pad Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 Coordinate X 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 Y 630 755 880 1005 1130 1255 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
100-TQFP (S6B2107)
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44
S6B2107
(100-TQFP)
C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R
6
DIO1 FS DS1 DS2 C NC R NC CR NC SHL VSS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 NC CL2 NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP)
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44
Y
(0, 0)
X
Chip size: 3850 x 4100 PAD size: 100 x 100 Unit : m
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R
VSS 37
MS 39
FS 27
M 44
C 30
R 32
DS1 28
DS2 29
SHL 36
CLK2 40
CLK1 41
DIO1 26
FRM 43
NOTE:
There is the mark S6B2107 on the center of the chip.
PCLK2 46
DIO2 47
CL2 49
CR 34
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES (100-TQFP)
Pad Number Pad Name Coordinate X Y Pad Number Pad Name Coordinate X Y Pad Number Pad Name Coordinate X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS DS1 DS2
-1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1245 -1095 -945 -795
1534 1409 1284 1159 1034 909 784 659 534 409 284 159 34 -91 -216 -341 -466 -591 -716 -841 -966 -1091 -1216 -1341 -1466 -1821 -1821 -1821 -1821
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 CL2 PCLK2 DIO2 FRM M MS CLK2 CLK1 SHL VSS
NC -195 0 NC 195 345 495 NC 645 795 NC 945 1095 NC 1245 NC 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 -1466 -1341 -1216 -1091 -966 -841 -716 -591 466 -341 -216 -91 34 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23
1697 1697 1697 1697 1697 1697 1697 1500 1375 1250 1125 1000 875 750 625 500 375 250 125 0 -125 -250 -375 -500 -625 -750 -875 -1000 -1125
784 909 1034 1159 1284 1409 1534 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
30 31 32 33 34
C
-645 NC
-1821
64 65
C56 C55 C54 C53 C52
1697 1697 1697 1697 1697
159 284 409 534 659
98 99 100
C22 C21 C20
-1250 -1375 -1500
1822 1822 1822
R
-495 NC
-1821
66 67
CR
-345
-1821
68
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
Table 1. Pin Description Pin Number QFP (TQFP) 28(25) 40(37) 23(20), 58(55) 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) Symbol VDD VSS VEE V0L, V1L, V4L, V5L, V0R V1R V4R V5R Power I/O Power Description For internal logic circuit (+5V 10%) GND ( = 0 V) For LCD driver circuit Bias supply voltage terminals to drive LCD.
Slelect Level V0L (R), V5L (R) Non-Select Level V1L (R), V4L (R)
V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should be connected by the same voltage. 42(39) MS Input Selection of master/slave mode - Master mode (MS = 1) DIO1, DIO2, CL2 and M is output state. - Slave mode (MS = 0) SHL = 1 DIO1 is input state (DIO2 is output state) SHL = 0 DIO2 is input state (DIO1 is output state) CL2 and M are input state. 39(36) SHL Input Selection of data shift direction.
SHL H L Data Shift Direction DIO1 C1 ...... C64 DIO0 DIO2 C64 ...... C1 DIO0
49(46)
PCLK2
Input
Selection of shift clock (CL2) phase.
PCLK2 H L Shift Clock (CL2) Phase Data shift at the rising edge of CL2 Data shift at the falling edge of CL2
30(27)
FS
Input
Selection of oscillation frequency. - Master mode When the frame frequency is 70 Hz, the oscillation frequency should be fosc = 430kHz at FS = 1(V DD) fosc = 215kHz at FS = 0(V SS) - Slave mode Connect to VDD.
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 31(28) 32(29) Symbol DS1 DS2 I/O Input Selection of display duty. - Master mode
DS1 L L H H DS2 L H L H Duty 1/48 1/64 1/96 1/128
Description
- Slave mode Connect to VDD 33(30) 35(32) 37(34) C R CR RC Oscillator - Master mode: Use these terminals as shown below.
S6B0107 R Rf CR Cf C R Open S6B0107 CR External C Open
- Slave mode: Stop the oscillator as shown below.
R Open CR VDD C Open
44(41) 43(40)
CLK1 CLK2
Output
Operating clock output for the S6B0108 - Master mode: connection to CLK1 and CLK2 of the S6B0108 - Slave mode: open Synchronous frame signal. - Master mode: connection to FRM of the S6B0108 - Slave mode: open Alternating signal input for LCD driving. - Master mode: output state Connection to M of the S6B0108 - Slave mode: input state Connection to the controller Data shift clock - Master mode: output state Connection to CL of the S6B0108 - Slave mode: input state Connection to shift clock terminal of the controller. Data input/output pin of internal shift register.
MS H DS2 H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input
46(43)
FRM
Output
47(44)
M
Input/ Output Input / Output
52(49)
CL2
29(26) 50(47)
DIO1 DIO2
Input/ Output
L
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 22-1(19-1) 100-59(100-56) Symbol C1-C64 I/O Output Description Common signal output for LCD driving.
Data L L H H M L H L H Out V1 V4 V5 V0
34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50)
NC
No connection
MAXIMUM ABSOLUTE LIMIT Characteristic Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Operating temperature Storage temperature
NOTES: 1. Based on VSS = 0V 2. 3. 4. Applies to input terminals and I/O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)). Applies to V0L(R), V1L(R), V4L(R) and V5L(R). Voltage level: VDD V0L = V0R V1L = V1R V4L = V4R V5L = V5R VEE.
Value -0.3 - +7.0 VDD-19.0 - VDD+0.3 -0.3 - VDD+0.3 VEE-0.3 - VDD+0.3 -30 - +85 -55 - +125
Unit V V V V C C
Note
(1) (4) (1), (2) (3), (4)
TOPR TSTG
- -
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (V DD = +5V 10%, VSS = 0V, |V DD-VEE |=8 - 17V, Ta = -30 to +85C) Characteristic Input Voltage Output Voltage High Low High Low Symbol VIH VIL VOH VOL ILKG fOSC RON IOH = -0.4mA IOL = 0.4mA VIN = VDD-VSS Rf = 47k 2% Cf = 20pf 5% On resistance (VDIV-CI) VDD-VEE = 17V Load current = 150A Operating current IDD1 IDD2 Supply current Operating Frequency IEE fop1 fop2 Master mode 1/128 Duty Slave mode 1/128 Duty Master mode 1/128 Duty Master mode External clock Slave mode - - - 50 0.5 - - - - - 1.0 200 100 600 1500 kHz mA A
(3)
Condition -
Min 0.7V DD VSS VDD-0.4 - -1.0 315
Typ - - - - - 450
Max VDD 0.3V DD - 0.4 1.0 585
Unit V
Note
(1)
V
(2)
Input leakage current OSC frequency
A kHz
(1)
-
-
1.5
K
(4)
(5)
NOTES: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M and CL2 in the input state. 2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M and CL2 in the output state. 3. This value is specified at about the current flowing through VSS. Internal oscillation circuit: Rf = 47k, Cf = 20pF Each terminal of DS1, DS2, FS, SHL and MS is connected to VDD and out is no load. 4. is connected to VDD, and MS is connected to VSS. CL2, M, DIO1 is external clock. 5. This value is specified at about the current flowing through VEE. Don't connect to VLCD (V1-V5). This value is specified at about the current flowing through VSS. Each terminal of DS1, DS2, FS, SHL, PCLK2 and CR
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
AC CHARACTERISTICS (VDD = 5V 10%, TA = -30C to +85C) Master Mode (MS = VDD, PCLK2 = VDD, Cf = 20pF, Rf = 47k)
CL2
0.7VDD 0.3VDD
tWLC tWHC tDH
tsu
t su
tW H C
DIO1 (SHL = V D D) DIO2 (SHL = V SS) DIO2 (SHL = V D D) DIO1 (SHL = V SS) tD
tD
tDF
FRM
tDM tDM 0.7VDD 0.3VDD tF tR tWH1
M
CLK1
tWL1
tD12
tD21
CLK2
tWH2 tF tR
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
Master Mode
Characteristic Symbol Min Typ Max Unit s
Data setup time Data hold time Data delay time FRM delay time M delay time CL2 low level width CL2 high level width CLK1 low level width CLK2 low level width CLK1 high level width CLK2 high level width CLK1-CLK2 phase difference CLK2-CLK1 phase difference CLK1, CLK2 rise/fall time
tSU tDH tD tDF tDM tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/tF
20 40 5 -2 -2 35 35 700 700 2100 2100 700 700 -
- - - - - - - - - - - - - -
- - - 2 2 - - - - - - - - 150
ns
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Slave Mode (MS = VSS)
tF
tR
tWLC1 tWHC1 tSU tWHC2 tWLC 0.7VDD 0.3VDD
CL2 (PLK2 = V SS)
CL2 (PLK2 = VDD)
tR tF tD 0.7VDD 0.3VDD tH 0.7VDD 0.3VDD tHCL
DIO1 (SHL = V DD) DIO2 (SHL = V SS) Input Data DIO1 (SHL = V DD) DIO2 (SHL = V SS) Onput Data
Characteristics CL2 low level width CL2 high level width CL2 low level width CL2 high level width Data setup time Data hold time Data delay time Output data hold time CL2 rise/fall time
NOTE: Connect load CL = 30pF
Symbol tWLC1 tWHC1 tWLC2 tWHL tSU tDH tD tH tR/tF
Min 450 150 150 450 100 100 - 10 -
Typ - - - - - - - - -
Max - - - - - - 200 - 30
Unit ns ns ns ns ns ns ns ns ns
Note PCLK2 = VSS PCLK2 = VSS PCLK2 = VDD PCLK2 = VDD
(NOTE)
Output 30pF
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
FUNCTIONAL DESCRIPTION RC Oscillator The RC Oscillator generates CL2, M, FRM of the S6B0107, and CLK1 and CLK2 of the S6B0108 by the oscillation resister R and capacitor C. When selecting the master/slave mode, the oscillation circuit is as following: Master Mode: In the master mode, use these terminals as shown below.
S6B0107 R Rf 47K CR Cf 20pF Open Open External Clock External Clock C R S6B0107 CR C
Internal Oscillation
Slave Mode: In the slave mode, stop the oscillator as shown below.
S6B0107 R Open VD D CR C Open
Timing Generation Circuit It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit. Selection of Master/Slave (M/S) Mode - When M/S is "H", it generates CL2, M, FRM, CLK1 and CLK2 internally. - When M/S is "L", it operates by receiving M and CL2 from the mater device Frequency Selection (FS) To adjust FRM frequency by 70Hz, the oscillation frequency should be as follows: FS H L In the slave mode, it is connected to VDD. Oscillation Frequency fOSC = 430kHz fOSC = 215kHz
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 L DS2 L H H L H DUTY 1/48 1/64 1/96 1/128
Data Shift & Phase Select Control Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to PCLK2. PCLK2 H L Phase Selection Data shift on rising edge of CL2 Data shift on falling edge of CL2
Data Shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS H SHL H L L H L DIO1 Output Output Input Output DIO2 Output Output Output Input C1 C64 C64 C1 DIO1 C1 C64 DIO2 DIO2 C64 C1 DIO1 Direction of Data
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
TIMING DIAGRAM
1/48 DUTY TIMING (MASTER MODE) Condition: DS1 = L, DS2 = L, SHL = H(L), PCLK2 = H
C CLK1 CLK2 2 3 ~ ~ 1 2 3
~~ ~~ 63 ~ ~ 46 47 48 1 2 3 ~ ~ 46 47 48 64
1 CL2 FRM DIO1 (DIO2) M C1 (C48) C2 (C47) V1
~ ~ ~~ ~~ V4 V4 ~ ~ V5 ~ ~
~ ~ ~ ~ ~ ~ V1 V1 V0 ~ ~
V1
V4
V0
V1 V5 V0
V4
~ ~
V1 C47 (C2) C48 (C1) DIO2 (DIO1) V5 V1 V5
V4 ~ ~ V4 ~ ~ ~ ~ ~ ~
V4 V0
V1 V1
V1 ~ ~ V5 ~ ~ V5 ~ ~
V4 V4
Relation of CL2 & DIO1 (DIO2)
~ ~ CLK2
~ ~
CL2
~ ~ ~ ~ ~ ~
DIO1 (DIO2)
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
1/128 DUTY TIMING (MASTER MODE) Condition: DS1 = H, DS2 = H, SHL = H(L), PCLK2 = H
C CLK1 CLK2 1 CL2 FRM DIO1 (DIO2) M C1 (C128) C2 (C127) V1 V1 V4 V0 ~ ~ V0 V4 ~ ~ V4 ~ ~ V5 V1 ~ ~ V1 V5 V0 V4 ~ ~ V4 ~ ~ V4 V0 V1 V1 ~ ~ V5 ~ ~ ~ ~ V5 V4 V4 2 3 ~ ~ 126 127 128 1 2 3 ~ ~ 126 127 128 1 2 3 23 24
~ ~ ~~ ~~
~ ~ ~ ~ ~ ~ V1 V0 V1
V1 C127 (C2) C128 (C1) DIO2 (DIO1) V5 V1 V5
V4
~ ~ ~ ~
Relation of CL2 & DIO1 (DIO2)
~ ~ CLK2
~ ~
CL2
~ ~ ~ ~ ~ ~
DIO1 (DIO2)
20
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
1/48 DUTY TIMING (SLAVE MODE) Condition: PCLK2 = L, SHL = H(L)
1 CL2
2 ~ ~ ~ ~
46
47
48
1
2 ~ ~
46
47
48
M ~ ~
DIO1 (DIO2) ~ ~ ~ ~ V1 C1 (C48) ~ ~ V0 ~ ~ V4 V5 V1
V0
V1 C2 (C47) V4
V0 ~ ~ V4 ~ ~ V5 V0 V1
V1 V4
V1 C47 (C2) V4 ~ ~ V4
V1 ~ ~
V1 V4 V5
V0 V4 ~ ~ C48 (C1) V5
V1 ~ ~ V4 V5
DIO2 (DIO1) ~ ~ ~ ~
21
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
POWER DRIVER CIRCUIT
VD D
V0 V0L/R R1 R1 R2 V3 R1 V4 R1 V5 VR V5L/R V4L/R V1 V1L/R V2 To S6B0108
VD D
S6B0107
VEE
VEE
Relation of Duty & Bias Duty 1/48 1/64 1/96 1/128 Bias 1/8 1/9 1/11 1/12 RDIV R2 = 4R1 R2 = 5R1 R2 = 7R1 R2 = 8R1
When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1 + R2) = 1/8 R1 = 3k, R2 = 12k
22
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
APPLICATION CIRCUIT 1/128 duty segment drive (S6B0108) interface circuit
V0R/L
V2R/L
V3R/L
V5R/L
V0R/L
V2R/L
V3R/L
CLK1
CLK2
CLK1
CLK2
FRM
FRM
CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS VDD
SEG128
V5R/L CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS VSS VDD
VEE
VEE S1 - S 64
CL
S1 - S64
15
S6B0108
VSS
LCD Panel
V0R/L V2R/L V3R/L V5R/L V0R/L V2R/L V3R/L V5R/L VEE VEE
M
M
COM1
COM128
5
5
open open
PCLK2
R DS1 DS2 PCLK2 MS FS SHL V0R/L V1R/L V4R/L V5R/L VDD VSS VEE
DIO2
CLK2 CL2 M 2
S6B0107 (master)
CL2 M CLK2 CLK1 FRM
S6B0107 (slave)
open open open open open
R1
CLK1 FRM C CR R
V0R/L
V1R/L
V4R/L
V5R/L
VDD
VEE
VSS
5
MS
VDD
VDD
V0
V1
V2
V3
V4
V5
VEE
C1
C CR
DIO1
DIO2
SHL
C1
C1
C64
C64
FS
DS1
KS2
RS R/W E RSTB DB0 - DB7 CS1B CS2B CS3
CLK1
CLK2
CLK1
CLK2
CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS FRM VDD
S1 - S64
15
S6B0108
S1 - S64
S6B0108
CL
M
M
FRM
VSS
VDD
CL
CL
CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS VSS
15
S6B0108
15
SEG1
MPU
15
23

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